1. Field of the Invention
This invention relates to the manufacture of integrated circuits and more particularly to the manufacture of microcontrollers having "on-chip" memory devices.
2. Description of Related Art
A typical computer system includes a microprocessor secured within a semiconductor device package and connected via signal lines to several separately-packaged support circuits. These support circuits typically include one or more memory devices and circuits which perform an interface function between the microprocessor and the one or more memory devices. A microcontroller is an integrated circuit which incorporates a microprocessor core along with one or more support circuits on the same monolithic semiconductor substrate (i.e., chip). Computer systems which employ microcontrollers may thus be formed using fewer semiconductor devices. Advantages of such systems include lower fabrication costs and higher reliabilities. Various microcontrollers include memory interface circuits and one or more memory devices along with a microprocessor core on the same chip. Microcontrollers find applications in industrial and commercial products including control systems, computer terminals, hand-held communications devices (e.g., cellular telephones), photocopier machines, facsimile machines, and hard disk drives.
FIG. 1 is a block diagram of an exemplary microcontroller 10 including a microcontroller core 12 coupled to an "on-chip" memory device 14 and to several input/output (I/O) pads 16. During manufacture of microcontroller 10, signal lines to be connected to external devices are terminated at I/O pads 16. I/O pads 16 are flat metal contact regions located upon an exposed surface of the chip. Following manufacture, microcontroller 10 is typically secured within a protective semiconductor device package. Each I/O pad is then connected to a terminal (i.e., pin) of the device package by a signal line (i.e., a wire).
Microcontroller core 12 includes a microprocessor core 18 and memory interface circuitry 20. Microprocessor core 18 is configured to execute microprocessor instructions, for example instructions from an x86 instruction set. Memory interface circuitry 20 generates control signals which enable the storing of data within and the retrieving of data from memory device 14 as well as any other memory devices connected to I/O pads 16. Operations within microcontroller 10 are synchronized by a system "clock" signal.
Testing of a memory device such as memory device 14 is typically accomplished by storing data within (i.e., writing to) the memory device, subsequently retrieving the stored data (i.e., reading) the data from the memory device, and comparing the retrieved data to the stored data. If the retrieved data matches the stored data, the memory device is working properly. As on-chip memory device 14 is typically not accessible for testing via I/O pads 16, microcontroller core 12 may be used to test the functionality of memory device 14.
A problem arises when microcontroller core 12 is used to test memory device 14 and the testing requires that the frequency of the clock signal be altered. If the frequency of the clock signal must be increased beyond the operational capability of microcontroller core 12 in order to test the functionality of memory device 14, microcontroller core 12 cannot be used to carry out the testing. This may occur, for example, when memory device 14 is a static random access memory (SRAM) device having memory cells with load devices, and the functionality of the load devices are to be tested.
FIGS. 2-5 will now be used to describe how a typical SRAM memory device operates, and how the functionality of the load devices is commonly tested. FIG. 2 is a block diagram of a typical SRAM device 30. SRAM device 30 includes a memory array 32, a row decoder 34, a column decoder/multiplexer 36, and a sense amplifier 38. Memory array 32 includes multiple memory cells, each of which store a single binary digit (i.e., bit) of data. The memory cells are typically arranged in a two-dimensional array with several rows and columns. Row decoder 34 receives m "row" address signals and produces 2.sup.m "row select" signals, one for each row in memory array 32. Each column of memory cells is associated with a complementary (i.e., differential) pair of signal lines referred to as "bit" and "bit'". Column decoder/multiplexer 36 receives n "column" address signals, selecting one of 2.sup.n bit and bit' pairs to provide to sense amplifier 38. As will be described in detail below, sense amplifier 38 senses a voltage difference between the bit and bit' signal lines, producing a data signal having a logic level which corresponds to the voltage difference. Memory cell 40 is one of the 2.sup.m+n memory cells within memory array 32.
FIG. 3 is a block diagram of a metal oxide semiconductor (MOS) memory cell 40 and sense amplifier 38 of FIG. 1. Memory cell 40 includes a pair of cross-coupled inverters 50a-b, forming a latch element having a pair of nodes 52a-b, and a pair of pass transistors 54a-b. Pass transistor 54a selectively couples node 52a of the latch element to the bit signal line, and pass transistor 54b selectively couples node 52b of the latch element to the bit' signal line. Both pass transistors 54a and 54b are controlled by the row select signal, being in a high resistance state (i.e., an "off" state) when the row select signal is deasserted, and being in a low resistance state (i.e., an "on" state) when the row select signal is asserted.
Inverter 50a includes an n-channel transistor 56a coupled between node 52a and a ground potential (i.e., "ground" or "V.sub.SS ") and a load device 58a coupled between node 52a and a positive power supply potential (i.e., "V.sub.DD "). Similarly, inverter 50b includes an n-channel transistor 56b coupled between node 52b and ground, and a load device 58b coupled between node 52b and V.sub.DD. Load devices 58a-b provide a current path from V.sub.DD to nodes 52a-b, respectively, allowing nodes 52a-b to be "charged" to V.sub.DD and to remain at V.sub.DD following such charging. Following charging of nodes 52a-b to V.sub.DD, current from V.sub.DD flowing through load devices 58a-b counteracts leakage currents from nodes 52a-b through the transistors connected thereto. Load devices 58a-b thus allow data stored within memory cell 40 to be retained as long as electrical power is supplied (i.e., "static" operation).
Sense amplifier 38 is used during read operations to detect a voltage difference between the bit and bit' signal lines and to produce a data signal having a logic level which corresponds to the voltage difference. Sense amplifier 38 includes a pair of cross-coupled inverters 60a-b, forming a latch element having a pair of nodes 62a-b, a pair of pass transistors 64a-b, and an inverter 66. Pass transistor 64a selectively couples node 62a of the latch element to the bit signal line, and pass transistor 64b selectively couples node 62b of the latch element to the bit' signal line. Both pass transistors 64a and 64b are controlled by a "control" signal, being in a low resistance "on" state when the control signal is deasserted, and being in a high resistance "off" state when the control signal is asserted.
FIG. 4 is a timing diagram illustrating signal timing during the reading of a logic high or "1" from memory cell 40 having functional load devices 58a-b. In this case, transistor 56a of the latch element of memory cell 40 is "off" and node 52a is substantially at V.sub.DD, and transistor 56b is "on" and node 52b is substantially at ground potential. Prior to or as the first step in a read operation, the bit and bit' signals lines are typically precharged to V.sub.DD. The row select signal is then asserted, connecting nodes 52a and 52b of the latch element of memory cell 40 to the bit and bit' signal lines, respectively. A relatively large capacitance typically exists between both the bit and bit' signal lines and ground. Transistor 56a is "off", and node 52a of the latch element of memory cell 40 remains at V.sub.DD. Transistor 56b is "on", and begins to discharge the capacitance of the bit' line. After a delay of time ".tau." to allow the difference in the voltage levels of the bit and bit' signals lines ("Vdiff") to reach a desired magnitude, the control signal is asserted, disconnecting node 62a of the latch element from the bit signal line and disconnecting node 62b of the latch element from the bit' signal line. The latch element of sense amplifier 38 changes state to indicate (i.e., "resolve") the corresponding logic value stored within memory element 40. The amount of time t required for this change of state is called the "resolve time" of sense amplifier 38, and is directly dependent upon the magnitude of Vdiff.
Should load devices 58a-b be missing or fail to perform correctly, nodes 52a-b cannot be fully charged to V.sub.DD. In addition, the leakage currents through the transistors connected to nodes 52a-b eventually cause the voltage at a charged node to drop below a logic level threshold value, causing the data stored within memory cell 40 to be lost. The operation of SRAM device 30 then becomes "dynamic" with a maximum allowable amount of time between write and read operations involving the same memory cell.
Even before data is lost due to charge leakage, the SRAM device may fail to perform correctly due to timing constraints. FIG. 5 is a timing diagram illustrating signal timing during the reading of a logic high or "1" from memory cell 40 having a non-functional load device 58a. As before, transistor 56a of the latch element of memory cell 40 is again "off". In this case, however, the voltage at node 52a is somewhere between (V.sub.DD -V.sub.tn) and 0 volts, where V.sub.tn is the threshold voltage of pass transistor 54a. The voltage at node 52a is dependent on the capacitance of node 52a, the magnitude of the leakage current from node 52a, and the amount of time since node 52a was charged. Receiving the voltage at node 52a, which is less than V.sub.DD, transistor 56b is not fully "on". When the row select signal is asserted, node 52a charges to (V.sub.DD -V.sub.tn) through transistor 54a. Since node 52a is connected to the gate electrode of transistor 56b and is not at V.sub.DD, transistor 56b has a higher internal resistance and discharges the capacitance of the bit' line at slower rate than shown in FIG. 4. After delay time .tau., the difference in the voltage levels of the bit and bit' signals lines ("Vdiff") is less than Vdiff of FIG. 4. As a result, the "resolve time" of sense amplifier 38 increases to t', where t'&gt;t. If the data signal is sampled before a time interval (.tau.+t'), the sampled value may be an incorrect value.
Microcontroller core 12 typically enables memory device 14 on a transition (i.e., "edge") of the system clock signal and samples and stores (i.e., latches) the data one or more full clock cycles later. When memory device 14 is an SRAM device, proper operation of the load devices within the memory cells may be tested by increasing the frequency of the system clock signal until the time interval between memory enable and data latch is less than (.tau.+t'). When this occurs, data retrieved from memory device 14 begins to differ from the data earlier stored within memory device 14.
This technique cannot be used, however, in cases where microcontroller core 12 fails to perform correctly at a system clock frequency below that at which memory device 14 fails to perform correctly (i.e., when memory device 14 is capable of "faster" operation than "slower" microcontroller core 12).
It would thus be desirable to have a microcontroller architecture and associated method which provide for testing of an "on-chip" memory device, wherein such testing does not require increasing the frequency of the system clock signal. Such a microcontroller architecture and method would be particularly useful in testing the functionality of load devices within memory cells of an on-chip SRAM memory device. The desired microcontroller architecture and method would allow a "slower" microcontroller core coupled to a "faster" on-chip memory device to test the functionality of load devices within the memory cells of the memory device.